![]() If the design uses functions from the altera.v library, add the library file name to the top of the Source Files list in the Synplify window. vhd) generated by the MegaWizard Plug-In Manager in your project. If you created and instantiated an LPM function in your design, you must also include the Verilog Design File (. To create a hierarchical project, select the top-level design file in the Files to Add to Project list and drag it to the bottom of the list. To add the files in the Files To Add To Project list in the Synplify window, click Add. Select one or more design files to add to the project in the Select Files to Add to Project dialog box. In the File Type list, select Project File (Project). To create and add files to a new project: ![]() To start the Synplify software on a Windows system, type synplify at a command prompt, or double-click the synplify.exe icon. To start the Synplify software on a Linux workstation, type synplify at a command prompt from your working directory. If you have not already done so, create a design for use with the Synplify software. To setup a project in the Synplify software: Setting up a project in the Synopsys Synplify software includes starting the Synplify software, creating the project and adding files, and selecting a target device and output settings. Setting Up a Project with the Synplify Software
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